The present invention relates to a semiconductor device and a technique for manufacturing the same. Particularly, the present invention is concerned with a technique applicable effectively to an electronic device (a semiconductor device) comprising a base member with an electronic part such as a semiconductor chip mounted on a main surface thereof and another wiring substrate stacked over the main surface of the base member.
Recently there has been a growing demand for the reduction in size of electronic devices such as semiconductor devices. Consequently, for diminishing a packaging area of a semiconductor device and a chip part mounted on a packaging substrate (mother board), it is considered effective to mount a plurality of electronic parts (semiconductor chips) on one electronic device (semiconductor device).
As a semiconductor device of such a configuration, a POP (Package on Package) type semiconductor device is being studied, in which a plurality of semiconductor chips are fabricated as separate packages and on one package is stacked another package, as disclosed, for example, in Japanese Unexamined Patent Publication No. 2007-123454 (Patent Document 1).
As a package configuration used in a POP type semiconductor device there is known, for example, the configuration illustrated in FIGS. 11 and 12 of Japanese Unexamined Patent Publication No. 2008-118152 (Patent Document 2). In Patent Document 2 there is used a wiring substrate comprising a wiring body formed on the substrate and conductor posts (conductor protrusions) provided on the wiring body. Further, an IC chip is flip-chip-coupled to one surface of the wiring body and the IC chip and the conductor posts are covered and sealed with insulating resin on one surface of the substrate. Thereafter, the resin is subjected to grinding to expose end faces of the conductor posts.